1. Field
The embodiments described herein relate to circuits and a methods for decoding column addresses in a semiconductor memory apparatus and more particularly, to circuits and a methods for decoding column addresses in a semiconductor memory apparatus so as to increase the speed of a parallel test and thereby shorten a test period.
2. Background
In a conventional semiconductor memory apparatus individual memory cells are activated for data input and output operations by activating associated word (or row) and column select lines. The word select lines are designated by row addresses and the column select lines are designated by column addresses. Often, conventional semiconductor memory apparatus are divided into parallel banks of cells. Accordingly, a conventional semiconductor memory apparatus is accessed by activating one of the plurality of memory banks, and then enabling the appropriate column select line.
In a multi-bank active operation, such as in a parallel test mode, a plurality of memory banks are all activated, and a data write operation is implemented in a manner such that the column select lines designated by column addresses are enabled one by one in each memory bank. The write test period can be shortened using such a parallel test mode, since the plurality of memory banks are simultaneously activated. However, in this case, the advantage obtained by the shortening of the test period is not substantial, even though the plurality of memory banks are activated in parallel This is because the column select signals are activated one by one in each memory bank, which still takes time.
In order to decode column addresses, a conventional semiconductor memory apparatus includes a predecoder, a main decoder and a pulse generation unit. The predecoder has a plurality of (for example, 3) predecoding sections for decoding 2 or 3-bits of plural-bit (for example, 8-bit) address. The main decoder implements a decoding operation using the pulse signal provided from the pulse generation unit. A column address decoding circuit of a conventional semiconductor memory apparatus configured in this way does not have any structure for recognizing the parallel test mode. Therefore, even in the parallel test mode, as in the normal operation, the operation is implemented in such a way as to enable the column select signals one by one. As a result, in a conventional semiconductor memory apparatus, the advantage obtained by shortening of the test period through realization of the parallel test mode is not substantial, and a technical limit exists in shortening the test period by conducting a parallel test.